An embodiment of the present invention relates to a semiconductor device, and more specifically, to a semiconductor device and method for manufacturing the same including a bit line.
Recently, although a semiconductor memory device, specifically, a Dynamic Random Access Memory (DRAM), is required to have large capacity, the increase in the number of DRAM cell per a given wafer size has been limited due to a restriction in the increase of the chip size. If the chip size is increased, the number of chips per wafer is decreased and the productivity of the device is reduced. As a result, the cell layout has been recently changed to reduce the cell area and research into integrating more memory cells into one wafer has been ongoing.
In order to protect the sidewalls of a bit line, spacers including a nitride film have been widely used. However, since the nitride film has a high dielectric constant, a parasitic capacitance is increased in the bit line.
Moreover, when forming a storage node contact and a bit line, two storage node contacts are formed at one time. While a damascene process is performed to form the bit line, the storage node contact is separated into two contacts. However, when a storage node contact hole is etched, an overlay process is employed to decrease contact resistance between a storage electrode and a source region. Also, when bit line tungsten is formed by a damascene process, a tungsten etch-back process is included. In the tungsten etch-back process, polysilicon of the storage node contact plug is etched together.